1. Field of Invention
Some embodiments of the present invention relate to techniques for operating a switched-capacitor circuit with reduced modulation of a reference signal. Some embodiments of the present invention relate to techniques for charging a capacitor of a switched-capacitor circuit in a manner that is input and feedback independent. More particularly, embodiments relate to methods and apparatuses for operating a switched-capacitor circuit in a manner that reduces or eliminates input signal dependence of a charge drawn from a reference voltage source.
2. Discussion of the Related Art
Analog and digital signal processing circuits may include switched-capacitor circuits to perform sampling or other operations on signals. For example, switched-apparatus circuits can be used in analog-to-digital converters and phase-locked loops (PLLs).
One type of switched-capacitor circuit includes a capacitor coupled to a ground and to an input by a switch, and to an output by another switch. When a first switch to the input is closed and a second switch to the output is open, during what is sometimes termed a “sampling phase,” the capacitor is charged by an input signal applied to the input. When the states of the switches are reversed, such that the first switch to the input is open and a second switch to the output is closed, during what is sometimes termed a “transfer phase,” the charge will flow out of the capacitor to the output.
Different switched-capacitor circuits may be implemented that include additional circuitry to perform operations on an input signal, or to receive other input signals. For example, switched-capacitor circuits may be implemented that apply a positive or negative gain to an input signal, integrate an input signal, find a difference between an input signal and a reference voltage, and integrate a difference between an input signal and a reference voltage, among other operations.
FIG. 1 shows one example of a switched-capacitor circuit that may be implemented to perform operations on an input signal. Specifically, the circuit 100 of FIG. 1 is arranged to perform an integration of a difference between an input signal Vin and a reference voltage Vref supplied by a source 120. The circuit 100 includes a first capacitor 102 that is connected to the input Vin and the reference voltage Vref via two pairs of switches S1, S4 and S2, S3. The circuit 100 also includes an integrator 110, which includes an operational amplifier (op-amp) 106 and a second capacitor 104.
Timing signals φ1 and φ2 are applied to the pairs of switches S1, S4 and S2, S3, as shown in FIG. 2. The signals are applied to control terminals of the switches such that the pairs of switches are switched open and closed in a non-overlapping manner; i.e., one pair is open when the other is closed.
The circuit 100 of FIG. 1 operates in the sampling phase while timing signal φ1 is high and the switches S1 and S4 are closed. During the sampling phase, capacitor 102 charges with the input signal Vin to acquire a charge equal to C1Vin. At the end of the sampling phase, φ1 goes low and φ2 goes high, starting the integration phase. During the integration phase, an amount of charge C1(Vref−Vin) is added to (or discharged from) the capacitor, based on the relationship between Vref and Vin. Also during the integration phase, the capacitor 102 is connected to the integrator 110 to charge/discharge the capacitor 104.
Over a period of cycles (each cycle including a sampling phase and an integration phase), the capacitor 104 and op-amp 106 operate to provide a signal Vout representing an integrated difference between Vin and Vref over the period of cycles. At the end of cycle n, the charge on the capacitor 104 is:C2Vout(n)=C2Vout(n−1)−C1(Vref−Vin)   (1)and, assuming that the op-amp 106 is ideal (infinite gain and infinite bandwidth) and the source 120 has zero output impedance, the output voltage Vout(n) is:Vout(n)=Vout(n−1)+(C1/C2)*(Vin(n)−Vref)   (2)
It is not always possible to assume zero output impedance for the source 120 of the reference voltage Vref. Additionally, at the start of the integration phase, the amount of charge added to or removed from the capacitor 102 is equal to C1(Vref−Vin), which is dependent on the input signal Vin provided to the capacitor 102 during the sampling phase; specifically, the amount of charge is dependent on the amount of charge previously supplied from Vin and its difference with Vref. The amount of charge from Vin stored by capacitor 102 also contributes to modulation of the reference voltage Vref when switch S2 connects Vref to capacitor 102.
If the source of reference voltage Vref has a settling time greater than the length of the switching signal φ2 (and greater than the integration phase), then the modulation affects the amount of charge added to (or discharged from) the capacitor 102, and an incorrect amount of charge will be added to (or discharged from) the capacitor 102. The error in the amount of charge transferred is dependent on the amount of charge stored in the capacitor 102 by the input signal Vin.
The error in the amount of charge transferred affects proper integration by the integrator 110 and could result in an integrator gain error. This integrator error could also affect the output of the circuit 100 over one or more cycles. For example, the error can cause an undesirable linearity error in an analog-to-digital converter. Some alternative circuits have been proposed to reduce the error.
FIG. 3 shows one circuit that has been proposed to alleviate signal-dependent charge errors in circuit 100 of FIG. 1. Circuit 300 of FIG. 3 uses a second capacitor 303 for the reference voltage Vref, different from the capacitor 320 used for the input signal Vin. During the sampling phase φ1, the capacitor 303 is discharged to ground entirely (as shown by two switches coupled between the capacitor 303 and ground, operating based on signal φ1), transferring out all previous charge stored therein. During each integration phase φ2, a constant amount of charge is delivered to the capacitor 303. The constant amount of charge drawn from Vref is thus independent of signal Vin as in circuit 100 of FIG. 1 (where the amount was dependent on Vin and the difference). This constant amount could be correct in each cycle. The integrator, comprising operational amplifier 306 and capacitor 304, operates as described above with respect to the integrator 110 of FIG. 1.
Circuit 400 of FIG. 4 has also been proposed to address the problems with circuit 100 of FIG. 1. The circuit 400 of FIG. 4 includes a first capacitor 402, to which is applied an input signal Vin, and a second capacitor 403, to which is applied an inverted form of input signal Vin provided by the inverter 415. During a sampling phase φ1, Vin and −Vin are respectively applied to capacitor 402 and capacitor 403. During phase φ2, the reference voltage Vref is applied to both capacitors 402, 403 and supplies a charge to (or removes a charge from) both.
Each capacitor 402, 403 may draw a signal-dependent charge from the reference voltage Vref, though because of the inverter 415 the capacitors 402, 403 are oppositely charged. The signal-dependent charges drawn from the reference voltage Vref are thus oppositely signed and would cancel one another. The source 420 of reference voltage Vref would thus see no impedance and would not be modulated, helping ensure that a correct amount of charge from Vref is added to the capacitor 402 during the phase φ2. The integrator 410 operates as described above with respect to the integrator 110 of FIG. 1.